Taipei, July 25, 2012 (CENS)--In face of Taiwan Semiconductor Manufacturing Co.'s (TSMC's) development of 3-dimension IC packaging for 20nm process technology it is working on, Taiwan's leading IC assemblers are vigorously boosting 3D IC packaging and test capacity.
The assemblers include Advanced Semiconductor Engineering Inc. (ASE), Siliconware Precision Industry Co., Ltd. and Powertech Technology Inc. Industry executives pointed out that the three are the most financially capable assemblers in Taiwan to invest in 3D IC R&D and manufacturing capacity.
ASE, currently the world's No.1 IC assembler by output capacity, said it has begun offering 2.5D packaging to 28nm processors, chipsets and baseband chips for personal computers and mobile phones. The company added that it will begin to deploy 3D IC packaging and test capacity sometime in the second half of this year in preparation for 2013 volume production.
Siliconware has applied for five hectares of land at the Central Taiwan Science Park as the site for its first 3D IC facility and other advanced factories such as package on package (PoP) and copper pillar bump (CPB) packaging and test facilities. The investment is estimated at NT$2 billion (US$66 million at US$1: NT$30).
Siliconware executives pointed out that the company will plan high capital expenditure over the next three years to boost advanced capacities to lure orders from smartphone, tablet PC, Ultrabook, cloud computing and hard disk drive IC sectors.
Powertech, which is currently the only Taiwanese assembler running through silicon via (TSV) packaging and test lines, will launch volume production of 3D IC packaging and test next year.
IC assemblers pointed out that although TSMC has begun deploying 3D IC packaging capability, it provides the service as total solution to only high-end customers such as Apple.
(by Ken Liu)